This invention generally relates to an encoder and, more particularly, to a serial encoder for encoding both data and necessary information for decoding the data.
In various applications sophisticated and complicated circuits are embodied in a single integrated circuit chip which are packaged in a form such that only a limited number of terminals or pins are available for interfacing with external circuitry, such as D.C. power and reference potential sources, sources of input signals to the integrated circuit and external circuits requiring output signals from the integrated circuit. The cost of manufacturing these integrated circuit packages increases significantly with increases in the number of terminals. Accordingly, it is desirable to minimize the number of terminals whenever possible. For similar reasons, it is desirable to minimize the number of terminals required by circuits mounted on printed circuit boards.
A common circuit element found in numerous circuits is a multistage binary memory, such as a binary counter. In many integrated circuits having such a binary memory, it is desired to transfer the data stored in the memory to circuitry external of the integrated circuit package. One known method of achieving this is to simply connect the output of each stage of the memory to a corresponding one of the integrated circuit pins. Needless to say, this method is not suitable for those applications in which the total number of pins available for access to the memory is less than the total number of stages.
Another known way of providing access to such a memory is to provide the memory data in serial form on a single pin. However, when the data is serialized, further information must be provided to distinguish between the different bits of the data stream and to correlate each output data bit with the associated stage of the memory. A known way of providing this decoding information is to employ another pin for providing the clock signal used to clock out the serial data to distinguish between the different bits and to employ another pin for providing the pulse which initiates the serial transfer of the data, so that the first data bit and thus subsequent data bits can be identified. While this approach has an advantage over the parallel method noted above whenever there are more than three memory stages, it still requires the use of three terminals.